From the 90 nm CMOS integrated circuit technique, Strain Channel Engineering with the purpose of enhancing carrier mobility of channel plays an increasingly important role with continuous reduction of a feature size of a device. A plurality of uniaxial process induced stress technology is used in device manufacturing process, that is, compressive stress or tensile stress is introduced in the channel direction so as to enhance the carrier mobility of channel and to enhance performance of the device. For example, for 90 nm process node, compressive stress in a PMOS device is provided by using embedded SiGe (e-SiGe) source/drain or using a (100) crystal orientation substrate in combination with a tensile stress contact etch stop layer (tCESL); for 65 nm process node, the first generation source/drain stress memorization technique (SMT×1) is further adopted on the basis of the 90 nm process node, for example, a dual contact etch stop layer is used; for 45 nm process node, the second generation source/drain stress memorization technique (SMT×2) is used on the basis of the previous technique, for example, e-SiGe technique may be used in combination with a tCESL or a dual CESL, besides, Stress Proximity Technique (SPT) may be used, moreover, a (110)-plane substrate is adopted for PMOS and a (100)-plane substrate is adopted for NMOS; after 32 nm process node, the third generation source/drain stress memorization technique (SMT×3) is used, for example, embedded SiC source/drain is used on the basis of the previous techniques to enhance the tensile stress in a NMOS device.
Moreover, technology of introducing stress to a channel can be realized by controlling a material or a cross-section shape of a channel or spacer apart from changing the materials of the substrate or source/drain. One example is that a dual stress liner (DSL) technique can be adopted. Another example is that a tensile stress SiNx layer spacer can be adopted for a NMOS and a compressive stress spacer can be adopted for a PMOS. Still another example is that the cross-section of the embedded SiGe source/drain is manufactured as a Σ-shaped so as to improve the channel stress in PMOS.
However, the effect of these conventional stress technologies is weakened increasingly with the continuous reduction in the size of devices. For a NMOS, dislocation and offset between the thin film layers providing stress become increasingly obvious with the reduction in the feature size, which requires providing higher stress precisely while the thickness of the thin films has to be thinned. For a PMOS, carrier mobility of channel in embedded SiGe source/drain technology significantly depends on the feature size, and thereby reduction in size compromises the effect of enhancing carrier mobility greatly.
The intrinsic stress in a silicon nitride thin film is caused by inherent nature that a nitrogen-centered network structure unit in a triangle plane trends to form a silicon-centered tetrahedron network structure having low-energy valence bonds. Due to the difference in valences of these two types of atoms, a strain occurs. For SiNxHy tensile stress generation obtained by a PECVD method using ammonia gas and silane as a reactant mixture, the process mainly comprises gas-phase formation of disilane and aminosilane groups, surface reaction of these plasma products and the subsequent release of redundant hydrogen performed on the subsurface through rejection reaction of hydrogen and ammonia gas. The extended Si . . . N bond formed in this densification process will be limited by the surrounding netted structure and is thus frozen into a tensile stress state effectively.
As compared with LPCVD, there are less rejection reactions in PECVD technique because the temperature of a substrate in the PECVD technique is relatively low, thus, there are more combinations containing hydrogen in the thin film, whereby flexibility of the netted structure is enhanced and the thin film stress is reduced. Therefore, a high-temperature cure process needs to be performed to generate a dehydrogenation densification process so as to enhance the thin film stress.
However, a relatively high-temperature cure process discharges more hydrogen element, which results in relatively high thin film tensile stress. But an excessively high temperature causes loss of the low-temperature advantage of PECVD and is unfavorable for the formed structures such as the MOSFET silicide and source/drain doping.
Thus, an ultraviolet-assisted thermal processing (UVTP) technology is used for treating PECVD silicon nitride so as to enhance the thin film stress. This technology uses the photon energy of ultraviolet to help breaking the Si bond and NH bond in the thin film. Hydrogen atoms in adjacent broken bonds combine with each other to form hydrogen gas in the molecule form, and hydrogen gas diffuses from the thin film to form dangling bonds and micropores in the thin film. The dangling bonds cross link with one another to make the micropores contract so as to obtain the minimal surface energy.
However, high-temperature cure and the UVTP dehydrogenation process may cause the whole silicon nitride thin film to be tensile stressed, in the meanwhile, the silicon nitride thin film needs to be combined with a low-temperature oxide (LTO) material or a low-k (low dielectric constant, e.g. k is no more than 3.9 or 2.8) material to form an ILD layer and to influence the total k value of the ILD layer. Besides, when tensile stress and compressive stress silicon nitride thin films are integrated simultaneously in a CMOS, a great challenge is confronted in selective etching. Therefore, it is of great significance to develop a novel high stress insulation thin film of a silicon oxide type.